1. Field of the Invention
The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly relates to a semiconductor memory device including a three-dimensional transistor and a manufacturing method of the semiconductor memory device.
2. Description of Related Art
The integration enhancement of semiconductor memory devices such as DRAM (Dynamic Random Access Memory) has been mainly achieved by downscaling the transistor size. However, the downscaling of transistors has almost reached its limit. If the transistor size is downscaled even more, it has a risk that the transistors do not operate correctly due to a short channel effect or the like.
In a conventional DRAM, a cell contact electrode to connect a cell capacitor and a cell transistor is provided to pierce through a bit line layer in which bit lines are formed. Therefore, the cell contact electrode needs to be securely dielectrically isolated from the bit lines. For this purpose, a SAC (Self Aligned Contact) etching technique using a silicon nitride film and a technique that forms a contact hole having smaller diameter than a resolution limit by using a side wall film (hole-pattern reduction technique) are used. However, the use of the SAC etching technique and the hole-pattern reduction technique has a problem of reducing a contact area of a bottom of the cell contact electrode.
As a measure of fundamentally solving such a problem, methods of three-dimensionally forming transistors by three-dimensionally processing a semiconductor substrate have been proposed. Particularly, a three-dimensional transistor that uses a silicon pillar extending in a vertical direction with respect to a main plane of the semiconductor substrate as a channel has an advantage of a small occupation area and can obtain a large drain current based on a complete depletion. The densest layout of 4F2 can be also achieved in this transistor (see Japanese Patent Application Laid-open No. 2009-010366).
When a vertical transistor using a silicon pillar is used as a cell transistor of a semiconductor memory device, one of diffusion layers that becomes a source or a drain is connected to a bit line, and the other diffusion layer is connected to a memory element (a cell capacitor in a DRAM). Normally, a memory element such as a cell capacitor is arranged above a cell transistor. Therefore, the memory element is connected to an upper part of the silicon pillar, and the bit line is connected to a lower part of the silicon pillar.
However, because a lower part of the silicon pillar is a semiconductor substrate, it is not necessarily easy to form a bit line at the lower part of the silicon pillar, and this requires a complex process in many cases. In this case, the bit line needs to be embedded into the semiconductor substrate. This results in a complex configuration and increases the parasitic capacitance of the bit line. Further, along with the downscaling of the transistor size, it has been difficult to secure a space to embed the bit line.
On the other hand, in conventional DRAMs as well as in DRAMs using a three-dimensional transistor, lithographic processing using an exclusive mask pattern is necessary to form a cell capacitor and a cell contact electrode. Therefore, the number of masks and the number of processes cannot be reduced and this results in cost increase.
Further, in conventional DRAMs as well as in DRAMs using a three-dimensional transistor, a memory cell is formed by processing each constituent element basically at a 2F pitch relative to the minimum feature size F. Therefore, only a memory cell having a cell area of 4F2 at minimum can be achieved, and this becomes a constraint to achieve further downscaling.